It is common for computer systems employing Dynamic Random Access Memories (DRAMs) to use DRAM modules which support symmetric addressing (i.e. wherein a row address propagated to a DRAM memory array has the same number of bits as a column address). A memory controller typically receives a memory address from an external resource, such as a Central Processing Unit (CPU), which the memory controller then decodes into a row address and a column address. Where the memory location addressed by the memory address is located, merely for example, in a one megabit deep DRAM module with symmetric addressing, the memory controller firstly propagates a 10-bit row address to the DRAM module, followed by a 10-bit column address. A number of memory controllers simply perform a predetermined mapping of bits of a memory address to respective row and column addresses. The configuration and size of a DRAM module which can be utilized in conjunction with such a memory controller is thus dictated by the mapping scheme implemented by the memory controller.
The use of DRAM modules having a single configuration across an entire memory array is limiting for a number of reasons. For example, when DRAM modules are in short supply on the market, computer manufacturers may desire to use DRAM modules of configurations that are readily available to implement a memory array. Thus, a need has arisen for a memory addressing scheme which allows a single memory controller to address a memory array comprised of DRAM modules of varying sizes and configurations. Further, for memory upgrade purposes, it is undesirable that the configuration of a DRAM module that can be utilized within a computer system be dictated by a pre-installed memory controller.